Method for manufacturing a semiconductor device

ABSTRACT

A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier layer is formed over the second conductive layer.

TECHNICAL FIELD

The invention relates generally to a method for manufacturing asemiconductor device, and more particularly, to a method formanufacturing a contact barrier layer of a semiconductor device.

BACKGROUND

There has been a trend in the semiconductor industry in increasing thepackaging density of wafers. The high integration level of semiconductorICs has been achieved by reducing the device dimension. Similar to otheraspects of integrated circuit processing, the technology for fabricatingcontacts has to evolve in order to keep up with the pace of otheradvancements in the process sequence.

A contact in a semiconductor integrated circuit allows electricalconnection between metal conductors and circuit elements in thesemiconductor integrated circuit substrate. In a common application forintegrated circuit fabrication, a dielectric layer is formed on asemiconductor substrate. A contact opening is etched through thedielectric layer to the semiconductor substrate. The contact opening isthen filled with a conductive material (e.g., titanium) to provide anelectrical connection between the metal conductors and the circuitelements. In order to prevent chemical reactions between the metalconductor and the substrate or between the metal conductors, a barrierlayer used as a barrier, such as a titanium nitride layer, is depositedover the conductive layer.

A well known process for depositing metal films is chemical vapordeposition (CVD). A commonly used method of forming a contact involvesthe application of a chemical vapor deposition titanium (Ti) processfollowed by a chemical vapor deposition titanium nitride (TiN) process.The CVD Ti deposition process is conducted at a high temperature, forexample between about 500° C. and 650° C., so that titanium silicide(TiSi₂) forms immediately when Ti layer is deposited. FIGS. 1A and 1Billustrate a method for manufacturing a contact. As shown in FIG. 1A, asemiconductor substrate 102 with a dielectric layer 104 and an opening106 are provided. A titanium layer 110 is then deposited by plasmaenhanced chemical vapor deposition (PECVD) as shown in FIG. 1B. Further,a titanium nitride barrier layer 114 is deposited prior to deposition ofcertain metal conductors 116 such as aluminum or tungsten. Titaniumnitride layer 114 is deposited by a chemical vapor deposition process. Atitanium silicide region 112 is formed due to the reaction of titaniumwith silicon.

SUMMARY OF INVENTION

In one embodiment of the present invention, a method for manufacturing asemiconductor device is disclosed. A semiconductor substrate such asbare silicon is provided, and a dielectric layer is formed over thesemiconductor substrate. An opening is provided within the dielectriclayer by removing a portion of the dielectric layer. A conformal firstconductive layer is formed over the dielectric layer and the opening. Aconformal second conductive layer is formed over the first conductivelayer. A conformal barrier layer is formed over the second conductivelayer.

In another embodiment of the present invention, a semiconductorsubstrate, such as bare silicon is provided, and a dielectric layer isformed over the semiconductor substrate. An opening is provided withinthe dielectric layer by removing a portion of the dielectric layer. Aconformal first conductive layer is formed over the dielectric layer andthe opening. An optional barrier layer is formed over the firstconductive layer. A conformal second conductive layer is formed over theoptional barrier layer. A conformal barrier layer is formed over thesecond conductive layer.

Still another embodiment of the present invention, a semiconductorsubstrate, such as bare silicon is provided, and a dielectric layer isformed over the semiconductor substrate. An opening is provided withinthe dielectric layer by removing a portion of the dielectric layer. Aconformal first conductive layer is formed over the dielectric layer andthe opening. An optional barrier layer is formed over the firstconductive layer. A conformal barrier layer is formed over the optionalbarrier layer.

BRIEF DESCRIPTION OF DRAWINGS

The foregoing summary, as well as the following detailed description,will be better understood when read in conjunction with the appended,exemplary drawings. It should be understood, however, that the inventionis not limited to the precise arrangements and instrumentalities shown.

FIGS. 1A to 1B are cross-sectional views illustrating a method formanufacturing a contact in the prior art.

FIGS. 2A-2C are cross-sectional views illustrating a method formanufacturing a contact barrier layer of a semiconductor deviceaccording to one embodiment of the present invention.

FIG. 3 is cross-sectional view illustrating a method for manufacturing acontact barrier layer of a semiconductor device according to anotherembodiment of the present invention.

FIG. 3A is a SEM picture of a contact barrier layer of a semiconductordevice according to an embodiment of the invention.

FIG. 4 is cross-sectional view illustrating a method for manufacturing acontact barrier layer of a semiconductor device according to anotherembodiment of the present invention.

FIG. 5 is a graph illustrating the contact resistance distributionaccording to one embodiment of the present invention.

DETAILED DESCRIPTION

Reference will now be made in detail to the exemplary embodiments of theinvention illustrated in the accompanying drawings. Wherever possible,the same reference numbers will be used throughout the drawings to referto the same or like. The following example embodiment shown in FIGS.2A-2C discloses a method of manufacturing a contact by forming a firsttitanium layer by applying a physical vapor deposition (PVD) processfollowed by forming a second titanium layer by applying a plasmaenhanced chemical vapor deposition (PECVD) process, and forming atitanium nitride (TiN) layer using a chemical vapor deposition (CVD)process to obtain a contact barrier layer with conformal step coverageand without overhang. The method of manufacturing a contact is describedin further detail below.

Referring to FIG. 2A, a semiconductor substrate 202 is provided. Thesemiconductor substrate 202 may be subjected to an ion-implantationprocess, thereby forming a heavily doped region (not shown), e.g., a P⁺well. A dielectric layer 204 is deposited or formed over thesemiconductor substrate 202. The semiconductor substrate 202 istypically bare silicon, but may be SiGe, or other semiconductormaterials. A portion of the dielectric layer 204 is selectively removedto provide an opening 206 within the dielectric layer 204. The opening206 may be patterned on the dielectric layer 204 by any of the variousphotolithography processes.

After the opening 206 is provided, the semiconductor device is loadedinto a physical vapor deposition (PVD) process chamber. In someembodiments, the PVD process chamber may be an ionized metal plasma(IMP) PVD process chamber or a self-ionized plasma (SIP) PVD processchamber. As illustrated in FIG. 2A, a first conductive layer 208, forexample, a first titanium layer (Ti layer) 208, is formed, and the firstconductive layer 208 may have a thickness between about 5 and 30Angstroms, for example. In some other embodiments, the thickness of thefirst titanium layer 208 may be within a range of 5 to 20 Angstroms, ormay be within a range of about 10 Angstroms to about 15 Angstroms. Thefirst titanium layer 208 is formed over the dielectric layer 204 as wellas the opening 206 by applying the IMP PVD process (i.e. IMP PVD Tiprocess). The formation of the first titanium layer 208 is achieved at atemperature, for example, within a range of 0° C. to 400° C., or withina range of 25° C. to 300° C. According to various applications, toobtain a conformal conductive layer 208, the temperature may varydepending on the thickness of the conductive layer 208.

In contrast with the deposition of the Ti layer using a chemical vapordeposition (CVD) process (i.e., CVD Ti process), a titanium silicide(TiSi₂) layer is not formed simultaneously with the Ti layer during thePVD process. In other words, the reaction of Ti with silicon (Si) at thetemperature of the PVD process may not be as active as the correspondingreaction associated with the CVD Ti process. Hence, the formation of theconformal first Ti layer 208 over the dielectric layer 204 is resulted.The IMP PVD Ti process is able to provide more uniform contactresistances by performing a relatively easier control deposition processin contrast with the CVD Ti process.

As the size of the semiconductor devices continuously decreases to thesub-micron range, the aspect ratio (i.e., the ratio of contact holedepth to contact hole width) of contact holes is increased, and the stepcoverage (i.e., the ratio of film thickness on the bottom of the contacthole to the film thickness on the sides of the contact hole) issue forthe contact hole becomes a bottleneck. In order to improve step coverageand reduce overhang (i.e., the amount of material deposited at the topcorners of the contact hole, which limits the amount of material thatcan be deposited within the contact hole), a second conductive layer210, for example, a second Ti layer 210, is formed over the firstconductive layer 208 as shown in FIG. 2B. For forming the second Tilayer 210, the semiconductor device is transferred from the PVD chamberto a chemical vapor deposition (CVD) chamber (e.g., a plasma enhancedchemical vapor deposition (PECVD) chamber). The surface of the first Tilayer 208 is exposed to the atmosphere during the transfer because thevacuum is broken. Such intake of oxygen may cause the surface resistanceof the first Ti layer 208 to rise; thus, the RC value of the IC deviceincreases. However, in this embodiment, Ti from the second Ti layer 210formed after the CVD process may absorb the atmospheric oxygen, whichthen lead to the second Ti layer 210 to have stable properties (e.g.film resistance, proper thickness and good conformity).

During the formation of the second Ti layer 210, a source gas (e.g.,TiCl₄) is introduced to the CVD chamber. The second Ti layer 210 may beformed to a thickness between about 5-400 Angstroms, preferably betweena range of 5-200 Angstroms, or a range of 50-100 Angstroms. Thetemperature at which the formation of the second Ti layer 210 isconducted may be controlled between about 350° C. to 650° C., or betweena preferable range of 500° C.-650° C. In some exemplary embodiments, thetemperature may be within a range of 600° C.-650° C. depending on theapplications. Since the CVD process for forming the second Ti layer 210is performed at a high temperature, a portion of the first Ti layer 208may react with the substrate material, thereby forming a titaniumsilicide (TiSi₂) layer 212 with low resistance on the portion of thesemiconductor substrate 202 exposed by the opening 206. A larger processwindow for the formation of the TiSi₂ layer 212 may therefore beobtained due to the inert reaction of titanium (from the first Ti layer208) with silicon (from the semiconductor substrate 202), which mayimprove the thermal stability of the TiSi₂ layer 212.

In order to prevent chemical reactions between the metal conductor andthe substrate or between the metal conductors, a barrier layer 214 isformed over the second Ti layer 210 as a barrier using the CVD processas illustrated in FIG. 2C. In one example, titanium chloride (TiCl₄) asa titanium source gas and ammonia (NH₃) as a reactant gas are suppliedat a predetermined flow rate to form a titanium nitride (TiN) layer asthe barrier layer 214. In this manner, titanium nitride (TiN) is formedfrom titanium chloride (TiCl₄) in reaction with ammonia (NH₃). In analternative example embodiment, a tantalum nitride (TaN) layer may serveas the barrier layer formed by using TiCl₅ as a titanium source. Invarious embodiments, a tungsten nitride (WN) layer or a titaniumtungsten (TiW) layer may serve as the barrier layer 214. In oneembodiment, the barrier layer 214 has a thickness between about 5 and500 Angstroms. In various embodiments, the thickness of the barrierlayer 214 may be between a range of 50 and 200 Angstroms or 70 and 150Angstroms. The CVD process may be performed at a temperature rangingfrom to 350° C. to 700° C. In other example embodiments, the temperaturemay range from 400° C. to 650° C. or preferably, from 600° C. to 650° C.Depending on applications, the thickness of the barrier layer and thetemperature of the formation may vary and optimize.

As shown in FIGS. 2A-2C, a first Ti layer 208 is formed over thedielectric layer 204 and the opening 206 using a PVD process and asecond Ti layer 210 is formed over the first Ti layer 208 by applying aCVD process. Subsequently, a barrier layer 214 (e.g., TiN or TaN layer)is formed over the second Ti layer 210 using a CVD process. Thiscombination of material layers may provide superior bottom coverage inaddition to providing improved conformal TiN/TaN layer coverage.Referring to FIG. 2C again, a metal layer 216 is formed over the barrierlayer 214 to fill the opening 206.

An optional thermal treatment (e.g., a rapid thermal process (RTP)) maybe provided after the formation of the barrier layer 214. Thesemiconductor device may be put in a chamber in which nitrogen isprovided at a temperature between about 500° C. and 700° C. In variousexemplary embodiments, the temperature may range from 550° C. to 650° C.or 600° C. to 650° C. In one exemplary embodiment, the thermal treatmentmay last about 20-180 seconds. In other embodiments, the thermaltreatment may be conducted for 30-120 seconds or 40-60 seconds.

The performance of the barrier layer 214 may be improved by forming anadditional optional barrier layer 218 sandwiched between the firstconductive layer 208 and the second conductive layer 210, as illustratedin FIG. 3. In one embodiment, a deposition of titanium nitride (TiN) isaccomplished using precursors, such as tetrakis(dimethylamino)titanium(TDEAT), tetrakis(dimethylamino)titanium (TDMAT),tetrakis(ethylmethylamido)titanium (TEMAT) or mixtures thereof, in areaction with ammonia (NH₃) under the metal-organic chemical vapordeposition (MOCVD) conditions of 350 to 550° C. The optional barrierlayer 218 may be subjected to nitrogen (N₂) or helium (He) plasmatreatment by flowing He at a predetermined rate into the chamber whereradio frequency (RF) energy is applied at about 500 to 1000 watts toform the plasma. Alternatively, the deposition of titanium nitride (TiN)may be sputtered using a self-ionized plasma (SIP) method under a roomtemperature of 400° C. with titanium and nitrogen as a source gas and areaction source, respectively. FIG. 3A is a picture taken by SEM(Scanning Electron Microscope) showing the structure of a contactbarrier layer according to an embodiment of the invention. As shown inFIG. 3A, the contact barrier layer includes an IMP PVD titanium layer ofabout 80 angstrom thick, a MOCVD titanium nitride layer of about 25angstroms thick and a TiCl₄ CVD titanium nitride layer of about 160angstroms thick. Further, the TiCl₄ CVD titanium nitride layer has acolumnar structure. Moreover, the above contact barrier layer shown inFIG. 3A has been subjected to the optional rapid thermal process atabout 650° C.

In an alternative embodiment as illustrated in FIG. 4, a conformalbarrier layer 214 may be produced by forming a first conductive layer208 over the dielectric layer 204 and the opening 206 using a PVDprocess with a thickness between about 10 and 400 Angstroms, preferablybetween about 200 and 300 Angstroms.

Then, prior to forming the barrier layer 214, an optional barrier layer218 is formed over the first conductive layer 208 by applying aself-ionized plasma sputtering process or a metal-organic chemical vapordeposition to a thickness of 5 to 100 Angstroms, preferably 10 to 50Angstroms.

An optional thermal treatment (e.g., a rapid thermal process (RTP)) maybe provided after the formation of the optional barrier layer 218. Thesemiconductor device may be put in a chamber in which nitrogen at atemperature between about 500° C. and 700° C. is provided. In variousexample embodiments, the range of the temperature may range from 550° C.to 650° C. or 600° C. to 650° C.

Subsequently, the barrier layer 214 (e.g., TiN or TaN layer) is formedover the optional barrier layer 218 using a CVD process. The barrierlayer 214 may have a thickness of 20-200 Angstroms or a thickness of 40to 100 Angstroms in another embodiment. This combination of the materiallayers may provide smooth bottom coverage; thus conformal barrier layeris provided. A metal layer 216 is then formed over the barrier layer 214to fill the opening 206.

FIG. 5 is a graph illustrating the contact resistance distributionaccording to one embodiment of the present invention. Here, the x-axisindicates contact resistance (in ohm), and the y-axis indicates thedistribution (%).

As shown in the graph of FIG. 5, the curves within 520 show that theP+/N resistance is increased so as to form a relatively longer tailshape in contrast with curves within 510. The curve 512 shows theresistance obtained under the condition that the first Ti layer 208 isformed to a thickness of 5˜30 Angstroms using an IMP PVD process, thesecond Ti layer 210 is formed to a thickness of 5˜400 Angstroms over thefirst Ti layer 208 using a PECVD process and the barrier layer of TiN214 is formed to a thickness of 5˜500 Angstroms over the second Ti layer214 according to one example embodiment of the present invention.

It will be appreciated by those skilled in the art that changes could bemade to the examples described above without departing from the broadinventive concept thereof. It is understood, therefore, that thisinvention is not limited to the particular examples disclosed, but it isintended to cover modifications within the spirit and scope of thepresent invention as defined by the appended claims.

1. A method for manufacturing a semiconductor device, the methodcomprising: providing a substrate; forming a dielectric layer over thesubstrate; Providing an opening within the dielectric layer; forming afirst conductive layer over the dielectric layer and the opening;forming a second conductive layer over the first conductive layer; andforming a barrier layer over the second conductive layer.
 2. The methodof claim 1, wherein the step in forming the first conductive layercomprises applying at least one of a physical vapor deposition, anionized metal plasma physical vapor deposition, and a self-ionizedphysical vapor deposition.
 3. The method of claim 1, wherein the firstconductive layer has a thickness between about 5 to 30 Angstroms.
 4. Themethod of claim 1, wherein at least one of the first conductive layerand the second conductive layer comprises titanium (Ti).
 5. The methodof claim 1, wherein the step of providing the opening within thedielectric layer comprises removing a portion of the dielectric layer.6. The method of claim 1, wherein the barrier layer comprises at leastone of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride(WN), and titanium tungsten (TiW) or combination of them.
 7. The methodof claim 1, wherein forming the barrier layer comprises forming thebarrier layer with titanium chloride (TiCl₄) and ammonia (NH₃).
 8. Themethod of claim 1, further comprising annealing the barrier layer in achamber including nitrogen.
 9. The method of claim 1 further comprisesforming an optional barrier layer sandwiched between the firstconductive layer and the second conductive layer.
 10. The method ofclaim 9, wherein the step of forming the optional barrier layercomprises applying one of a self-ionized plasma (SIP) method and ametal-organic chemical vapor deposition method to form the optionalbarrier layer with a thickness of about 5 to 100 Angstroms.
 11. Themethod of claim 9, wherein the optional barrier layer comprises titaniumnitride (TiN).
 12. The method of claim 10, wherein the SIP method isperformed at a temperature of about 400° C. with a titanium (Ti) target.13. The method of claim 10, wherein the SIP method is performed usingtitanium and nitrogen respectively as a gas source and a reactionsource.
 14. The method of claim 10, wherein the metal-organic chemicalvapor deposition method is performed with precursors comprising at leastone of tetrakis(dimethylamino)titanium (TDEAT, Ti[N(C₂H₅)₂]₄),tetrakis(dimethylamino) titanium (TDMAT, Ti[N(CH₃)₂]₄),tetrakis(ethylmethylamido)titanium (TEMAT, Ti[N(C₂H₅)₂]₄) and mixturesthereof.
 15. The method of claim 10, wherein the metal-organic chemicalvapor deposition method is performed at a temperature of about 350° C.to about 550° C.
 16. The method of claim 10, wherein the metal-organicchemical vapor deposition method is performed in a presence of helium(He) or helium with nitrogen (N₂).
 17. The method of claim 10, whereinthe optional barrier layer formed by the metal-organic chemical vapordeposition method is subjected to a nitrogen (N₂) plasma treatment or ahelium (He) plasma treatment with a radio frequency (RF) energy appliedat about 500 to about 1000 watts.
 18. The method of claim 1, furthercomprising forming a metal layer over the barrier layer to fill theopening.
 19. The method of claim 1, wherein the step of forming thesecond conductive layer over the first conductive layer comprisesapplying a plasma enhancement chemical vapor deposition.
 20. The methodof claim 1, wherein the step of forming the barrier layer over thesecond conductive layer comprises performing a chemical vapor depositionprocess.
 21. The method of claim 1, wherein the barrier layer is about 5to 500 angstroms thick.
 22. The method of claim 1, wherein the barrierlayer comprises at least one of titanium nitride (TiN), tantalum nitride(TaN), tungsten nitride (WN) or titanium tungsten (TiW) and acombination thereof.
 23. The method of claim 1, wherein the step offorming the barrier layer comprises an application of titanium chloride(TiCl₄) and ammonia (NH₃).
 24. The method of claim 1 further comprisingannealing the barrier layer in a chamber containing nitrogen.
 25. Themethod of claim 1 further comprising forming a metal layer over thebarrier layer to fill the opening.
 26. A semiconductor device,comprising: a substrate; a dielectric layer, having an openingconfigured therein, disposed on the substrate; a conductive layer,disposed on the substrate and in the opening; a first barrier layer,disposed on the conductive layer; and a second barrier layer, disposedon the first barrier layer.
 27. The semiconductor device of claim 26,wherein the conductive layer comprises a physical vapor deposited (PVD)titanium layer.
 28. The semiconductor device of claim 26, wherein theconductive layer comprises an ionized metal plasma (IMP) PVD titaniumlayer or a self-ionized plasma (SIP) PVD titanium layer.
 29. Thesemiconductor device of claim 26, wherein the conductive layer has athickness of about 10 angstroms to 400 angstroms.
 30. The semiconductordevice of claim 26, wherein the conductive layer has a thickness ofabout 200 angstroms to 300 angstroms.
 31. The semiconductor device ofclaim 26, wherein the first barrier layer comprises a self-ionizedplasma (SIP) PVD titanium nitride layer or a metal-organic chemicalvapor deposited (MOCVD) titanium nitride layer.
 32. The semiconductordevice of claim 26, wherein the first barrier layer has a thickness ofabout 5 to 100 angstroms.
 33. The semiconductor device of claim 26,wherein the first barrier layer has a thickness of about 10 to 50angstroms.
 34. The semiconductor device of claim 26, wherein the firstbarrier layer is treated by a rapid thermal process.
 35. Thesemiconductor device of claim 34, therein the rapid thermal process isconducted at about 650° C.
 36. The semiconductor device of claim 26,wherein the second barrier layer comprises a chemical vapor depositedtitanium nitride layer.
 37. The semiconductor device of claim 26,wherein the second barrier layer has a thickness of about 20 to 200angstroms.
 38. The semiconductor device of claim 26, wherein the secondbarrier layer has a thickness of about 40 to 100 angstroms.
 39. Thesemiconductor device of claim 26, wherein the second barrier layercomprises a columnar structure.
 40. The semiconductor device of claim 26further comprising an additional conductive layer disposed between thefirst barrier layer and the second barrier layer.
 41. The semiconductordevice of claim 40, wherein the additional conductive layer comprises atitanium layer formed with titanium chloride (TiCl₄) and ammonia (NH₃).42. A semiconductor device, comprising: a substrate; a dielectric layer,having an opening configured therein, disposed on the substrate; a firstconductive layer, disposed on the substrate and in the opening; a secondconductive layer, disposed on the first conductive layer; and a barrierlayer, disposed on the second conductive layer.
 43. The semiconductordevice of claim 42, wherein the barrier layer comprises a columnarstructure.
 44. The semiconductor device of claim 42 comprising anadditional conductive layer disposed between the second conductive layerand the first barrier layer.
 45. The semiconductor device of claim 44,wherein the additional conductive layer comprises a titanium layerformed with titanium chloride (TiCl₄) and ammonia (NH₃).
 46. Thesemiconductor device of claim 42, wherein the first conductive layercomprises a titanium layer formed with ionized metal plasma (IMP) PVD.47. The semiconductor device of claim 42, wherein the second conductivelayer comprises a titanium layer formed with titanium chloride (TiCl₄).48. The semiconductor device of claim 42, wherein the barrier layercomprises a titanium nitride layer formed with titanium chloride(TiCl₄).
 49. The semiconductor device of claim 42, wherein the firstconductive layer is about 10 to 400 angstroms thick.
 50. Thesemiconductor device of claim 42, wherein the second conductive layer isabout 5 to 100 angstroms thick.
 51. The semiconductor device of claim42, wherein the barrier layer is about 20 to 200 angstroms thick.